Error detecting codes such as Cyclic Redundancy Check (CRC) codes are commonly used to detect errors in data sent either in packets or blocks. A CRC-r is a linear, cyclic, r-bit check code that is appended to an original data block. A CRC-r code can typically guarantee detection of some small number of randomly-occurring single bit errors in the data block (e.g., up to 4) or a single burst with a length of up to r errors. The length of an error burst is defined as the number of bits from the first errored bit to the last errored bit in the string, including these first and last errored bits. The bits between the first and last errored bits in the burst can contain errors or valid data.
An error burst can be extended beyond an original error burst length due to transmission processing. Examples of such transmission processing include: de-interleaving data on a multi-lane data interface; feedback from a Decision Feedback Equalizer (DFE) receiver; and block line decoding, such as 8B/10B block line code decoding.
A DFE receiver uses feedback about the decisions it has made regarding the value of some number of received bits to allow a better decision regarding the value of the current received bit. While a DFE is very effective in removing the effects of some types of noise/impairments, the effects of an incorrect decision can propagate through the feedback mechanism to cause additional decision errors in some subsequently received bits. As a result, a single transmission channel bit error can be converted or multiplied into a burst of errors. DFE-receivers are one important source of error bursts.
Another source of error extension or multiplication is the decoding process of an 8B/10B block line code. The 8B/10B code is a block code that converts a block of 8 bits (e.g., a byte) into a 10-bit code for transmission. The most typical 8B/10B codes actually consist of two sub-codes, where the original eight bits are divided into a 3-bit and 5-bit pair of groups that are then encoded into a 4-bit and 6-bit pair of groups, respectively. The resulting 10-bit code has certain desirable properties such as limiting the number of consecutive data 0s or 1s that are transmitted, and achieving a running balance between the number of 0s and 1s that are transmitted. A property of 8B/10B decoding, however, is that a single transmission channel error will cause the entire sub-code to be improperly decoded, causing a burst of up to three or five bit errors. If the 8B/10B decoding is performed after a DFE receiver, the combination of the DFE and 8B/10B decoder error multiplication can further stretch the error burst.
In a multi-lane data interface, the interface data source interleaves the data across the multiple transmitters. The interleaving is typically done on a byte-by-byte basis (or 10-bit character basis if the 8B/10B line code is used). A 4-lane interface using byte/character interleaving is illustrated in FIGS. 1 and 2. FIG. 1 illustrates the manner in which data characters are interleaved and reassembled when going across a multi-lane interface. FIG. 2 illustrates points in an end-to-end connection at which the 8B/10B encoding/decoding and error check code insertion/checking are performed. In the example in FIG. 1, the characters that are sent over the first lane are shown in bold in order to highlight their relative positions in the data stream recovered after de-interleaving. If, in this example, an error burst occurs in the first lane that corrupts bytes 1 and 5, a burst of up to 16 bits is created at the output of that lane's receiver. However, the error burst in the re-assembled data block will be up to 40 bits long due to bytes 2-4 being re-inserted by the de-interleaving process. While a CRC-16, for example, is guaranteed to detect any error burst of up to 16 bits, it is not guaranteed to detect an error burst of up to 40 bits.
Error bursts that are spread by a multi-lane data interface are not specifically addressed by any existing error detecting code. An advantage of the CRC is that it is relatively easy and economical to implement the CRC encoder and decoder. The only codes that are known to detect these longer error bursts are either CRC codes of longer length, or more complicated error-detecting codes such as the Reed-Solomon code. A longer-length CRC begins to consume too much bandwidth as the number of lanes increases. A CRC-40 would be required for the 4-lane example in FIGS. 1 and 2, and a CRC-272 would be required for a 16-lane interface. The more complicated error-detecting codes add significant complexity and power consumption to the circuits.
Currently identified CRC codes have very limited capability for detecting extended error bursts such as can be created through byte/character de-interleaving on multi-lane data interfaces. The problem is more severe when 8B/10B block line codes are used. When DFE receivers are used on each data lane, error bursts become more common since the bursts can be induced by a single line error. Only significantly longer CRC codes or more powerful/complex codes are known to work. One problem is to identify a CRC capable of detecting these error bursts such that the new CRC code is no longer than the CRC originally chosen for the packet. The original CRC is typically a CRC-16 or CRC-32, but can be a length optimized for the application (e.g., a CRC-13).
As data interface rates increase, both parallel data lanes and DFE receivers are becoming increasingly important. Existing error detecting codes have not been created to handle the error bursts and extended error bursts that can result from this combination, especially when block line codes are being used. It is, therefore, desirable to provide error detection that is capable of detecting the types of extended error bursts that can result from DFE receiver mis-decoding, 8B/10B block decoding, and/or multi-lane data interface.